This invention relates to a device interface, especially in a programmable integrated circuit device, such as a programmable logic device (PLD), which may operate according to different interface standards.
A physical coding sublayer (PCS) interface included within a device processes data for transmission to, or that is received from, a physical medium attachment (PMA) coupled to an external device. PCS interfaces are often designed to support a specific PMA standard, for example, a CAUI or XLAUI standard.
Thus, one device may include a PCS interface designed to operate according to a XLAUI standard of 40 Gb/s using four physical lanes of 10 Gb/s each, while another device may include a PCS interface design to operate according to a CAUI standard of 100 Gb/s using 10 physical lanes of 10 Gb/s each. New standards continue to emerge. For example, a CAUI-4 standard uses four physical lanes at 25 Gb/s each. Emergent standards render obsolete older PCS interface designs and limit the applicability of any single PCS interface design. For example, high-end field programmable gate arrays (FPGAs) may be utilized in applications requiring high speed serial interfaces compliant with a wide range of standards based on 4×10 Gb/s, 10×10 Gb/s and 4×25 Gb/s Ethernet standards. Many PCS interfaces, however, are capable of operating only according to a single standard. Such. PCS interfaces may need to be largely redesigned as new standards emerge.